The components of the Packet Forwarding Engine fall into two main subsets:
1) Embedded OS software operating the circuit boards themselves
2) ASICs actually participating in packet forwarding.
As the router boots, the Embedded OS software (microcode) is downloaded from the Routing Engine to the CPUs on the circuit boards. Built by Juniper Networks engineers, the Embedded OS software contains a microkernel and individual threads that operate like the daemons on the Routing Engine.
Each circuit board in the Packet Forwarding Engine contains at least one ASIC, with some boards containing multiple chips.
PIC I/O Manager ASIC
Each PIC in the router contains an individual PIC I/O Manager ASIC that is unique to the specific media type on the PIC. For example, a PIC with Asynchronous Transfer Mode (ATM) interfaces has a different ASIC than a PIC with Synchronous Optical Network (SONET)/ Synchronous Digital Hierarchy (SDH) interfaces. The requirement for this individuality arises from the tasks of the ASIC.
The PIC I/O Manager ASIC handles media-specific tasks such as verifying data-link framing, detecting link-level errors, and generating link-level alarms.
I/O Manager ASIC
Each FPC contains a single I/O Manager ASIC that connects to both the PIC I/O Manager ASIC and the Distributed Buffer Manager ASIC on the control board. The I/O Manager ASIC performs multiple functions on each data packet.
As a data packet enters the router, the I/O Manager ASIC verifies the integrity of both the Layer 2 and Layer 3 headers. Provided the data packet is valid, the ASIC removes the Layer 2 header and segments the packet into 64-byte units called a J-cell. The I/O Manager ASIC sends these J-cells to the Distributed Buffer Manager ASIC for storage in the shared memory pool.
On the outgoing side of the router, the I/O manager queues a special J-cell called the result cell. The result cell contains the next-hop information for the packet as well as other information about which queue to store the packet in. When the router is ready to send the data packet out an interface, the I/O manager ASIC receives all of the packet’s J-cells from the packet buffer storage via the Distributed Buffer Manager ASIC.
Distributed Buffer Manager ASIC
Each control board in the router contains two Distributed Buffer Manager ASICs. The ASICs connect to the I/O Manager ASIC on the FPC and to the Internet Processor ASIC, which is also on the control board. The ASIC is logically split into two components, each with an important function. One of the ASICs, which we refer to as the Inbound Distributed Buffer Manager ASIC, is responsible for handling inbound J-cells. Its partner, the Outbound Distributed Buffer Manager ASIC, handles outbound J-cells.
Inbound Distributed Buffer Manager ASIC also generates a special J-cell called the notification cell. The notification cell contains information from the data packet, such as source and destination IP addresses, source and destination port numbers, the incoming interface on the router, Quality of Service (QoS) settings, and the existing protocol TTL value of the packet. The ASIC then sends the notification cell to the Internet Processor ASIC.
Internet Processor ASIC
Every Juniper Networks router contains a single Internet Processor ASIC on the control board in the Packet Forwarding Engine. In many respects, the Internet Processor ASIC is the heart of the Packet Forwarding Engine. It is the only ASIC in the forwarding path that accesses the forwarding table, performs route lookups, and makes forwarding decisions. It receives notification cells from the Inbound Distributed Buffer Manager ASIC and transforms them into result cells after performing a route lookup. Additionally, the Internet Processor ASIC performs firewall packet filtering, enforces policy controls on data packets, and collects exception packets for transmission to the routing engine.
Unicast Packet Flow
1. A data packet arrives on one of the router’s interfaces. The PIC I/O Manager ASIC formulates the packet and performs link-layer error checking, if appropriate.
2. The PIC I/O Manager ASIC transmits the data packet, complete with Layer 2 and Layer 3 headers, to the I/O Manager ASIC on its FPC.
3. The I/O Manager ASIC verifies the integrity of the Layer 2 and Layer 3 headers. Provided a valid protocol packet remains, the I/O Manager ASIC removes the Layer 2 header and segments the data packet into 64-byte J-cells. It then sends those J-cells to the Inbound Distributed Buffer Manager ASIC.
4. The Inbound Distributed Buffer Manager ASIC begins to receive J-cells from the I/O Manager ASIC. The notification cell is built and is transmitted to the Internet Processor ASIC.
5. The J-cells that make up the data packet are stored in the shared memory pool. Each FPC supplies the physical components of the shared memory, and the Inbound Distributed Buffer Manager ASIC sends the packet’s J-cells to all FPCs in the router on a round-robin basis.
6. The I/O Manager ASIC on each FPC receives the J-cells and stores them in its physical memory as instructed by the Inbound Distributed Buffer Manager ASIC.
7. While the J-cells are being stored in memory, the Internet Processor ASIC receives the notification
cell and performs a route lookup in the forwarding table. The next-hop router along the path of the route and the outgoing interface on the router is determined. This next-hop information is stored in the notification cell, which now becomes the result cell.
8. The Internet Processor ASIC sends the result cell to the Outbound Distributed Buffer Manager ASIC, which examines the cell to locate the outgoing interface. The result cell is then sent to the appropriate FPC for queuing and transmission.
9. The I/O Manager ASIC queues the result cell and applies appropriate queuing mechanisms. When the result cell reaches the head of the queue, the I/O Manager ASIC requests the packet’s J-cells from the Outbound Distributed Buffer Manager ASIC.
10. The Outbound Distributed Buffer Manager ASIC copies the J-cells from the packet storage buffer and sends them to the I/O Manager ASIC on the outgoing FPC.
11. The I/O Manager ASIC re-forms the data packet into a single unit and alters any protocol TTL values. The ASIC then appends the appropriate Layer 2 header information and sends the packet to the PIC I/O Manager ASIC.
12. The PIC I/O Manager ASIC performs any link-layer duties, if required, and transmits the data packet out the router’s interface.
Multicast Packets
A Juniper Networks router handles multicast data packets in a very similar fashion to unicast packets. There is only one major difference between the two, so we won’t repeat the packet flow steps in detail here.
Refer back to Figure 1.4 and the steps outlined in the previous section, and focus on steps 7 and 8. When the Internet Processor ASIC performs its route lookup on a multicast packet, it often finds multiple next-hop interfaces in the forwarding table. Information about all the outgoing interfaces is placed in the result cell and sent to the Distributed Buffer Manager ASIC. This ASIC examines the result cell and finds several outgoing interfaces. It generates a copy of the result cell for each interface and sends those cells to the appropriate I/O Manager ASICs on the FPCs. The queuing and transmission of the multicast packets at this point then follows the unicast packet steps outlined previously.
Exception Packets
The Packet Forwarding Engine can’t process some data packets in your network in its normal fashion. A prime example of these packets is routing protocol updates addressed to the router itself. There is no outgoing interface for these packets; they should be sent to the Routing Engine instead. The CPU on the router’s control board handles this type of traffic, called an exception packet.
Other forms of exception packets include:
-- Packets addressed to the router, such as ICMP pings, Telnet, and SSH traffic
-- Packets requiring the generation of an ICMP error message, including traceroute responses and destination unreachable messages
-- Packets containing an IP Options field
1) Embedded OS software operating the circuit boards themselves
2) ASICs actually participating in packet forwarding.
Embedded OS Software
As the router boots, the Embedded OS software (microcode) is downloaded from the Routing Engine to the CPUs on the circuit boards. Built by Juniper Networks engineers, the Embedded OS software contains a microkernel and individual threads that operate like the daemons on the Routing Engine.
Application-Specific Integrated Circuits
Each circuit board in the Packet Forwarding Engine contains at least one ASIC, with some boards containing multiple chips.
PIC I/O Manager ASIC
Each PIC in the router contains an individual PIC I/O Manager ASIC that is unique to the specific media type on the PIC. For example, a PIC with Asynchronous Transfer Mode (ATM) interfaces has a different ASIC than a PIC with Synchronous Optical Network (SONET)/ Synchronous Digital Hierarchy (SDH) interfaces. The requirement for this individuality arises from the tasks of the ASIC.
The PIC I/O Manager ASIC handles media-specific tasks such as verifying data-link framing, detecting link-level errors, and generating link-level alarms.
I/O Manager ASIC
Each FPC contains a single I/O Manager ASIC that connects to both the PIC I/O Manager ASIC and the Distributed Buffer Manager ASIC on the control board. The I/O Manager ASIC performs multiple functions on each data packet.
As a data packet enters the router, the I/O Manager ASIC verifies the integrity of both the Layer 2 and Layer 3 headers. Provided the data packet is valid, the ASIC removes the Layer 2 header and segments the packet into 64-byte units called a J-cell. The I/O Manager ASIC sends these J-cells to the Distributed Buffer Manager ASIC for storage in the shared memory pool.
On the outgoing side of the router, the I/O manager queues a special J-cell called the result cell. The result cell contains the next-hop information for the packet as well as other information about which queue to store the packet in. When the router is ready to send the data packet out an interface, the I/O manager ASIC receives all of the packet’s J-cells from the packet buffer storage via the Distributed Buffer Manager ASIC.
Distributed Buffer Manager ASIC
Each control board in the router contains two Distributed Buffer Manager ASICs. The ASICs connect to the I/O Manager ASIC on the FPC and to the Internet Processor ASIC, which is also on the control board. The ASIC is logically split into two components, each with an important function. One of the ASICs, which we refer to as the Inbound Distributed Buffer Manager ASIC, is responsible for handling inbound J-cells. Its partner, the Outbound Distributed Buffer Manager ASIC, handles outbound J-cells.
Inbound Distributed Buffer Manager ASIC also generates a special J-cell called the notification cell. The notification cell contains information from the data packet, such as source and destination IP addresses, source and destination port numbers, the incoming interface on the router, Quality of Service (QoS) settings, and the existing protocol TTL value of the packet. The ASIC then sends the notification cell to the Internet Processor ASIC.
Internet Processor ASIC
Every Juniper Networks router contains a single Internet Processor ASIC on the control board in the Packet Forwarding Engine. In many respects, the Internet Processor ASIC is the heart of the Packet Forwarding Engine. It is the only ASIC in the forwarding path that accesses the forwarding table, performs route lookups, and makes forwarding decisions. It receives notification cells from the Inbound Distributed Buffer Manager ASIC and transforms them into result cells after performing a route lookup. Additionally, the Internet Processor ASIC performs firewall packet filtering, enforces policy controls on data packets, and collects exception packets for transmission to the routing engine.
Unicast Packet Flow
1. A data packet arrives on one of the router’s interfaces. The PIC I/O Manager ASIC formulates the packet and performs link-layer error checking, if appropriate.
2. The PIC I/O Manager ASIC transmits the data packet, complete with Layer 2 and Layer 3 headers, to the I/O Manager ASIC on its FPC.
3. The I/O Manager ASIC verifies the integrity of the Layer 2 and Layer 3 headers. Provided a valid protocol packet remains, the I/O Manager ASIC removes the Layer 2 header and segments the data packet into 64-byte J-cells. It then sends those J-cells to the Inbound Distributed Buffer Manager ASIC.
4. The Inbound Distributed Buffer Manager ASIC begins to receive J-cells from the I/O Manager ASIC. The notification cell is built and is transmitted to the Internet Processor ASIC.
5. The J-cells that make up the data packet are stored in the shared memory pool. Each FPC supplies the physical components of the shared memory, and the Inbound Distributed Buffer Manager ASIC sends the packet’s J-cells to all FPCs in the router on a round-robin basis.
6. The I/O Manager ASIC on each FPC receives the J-cells and stores them in its physical memory as instructed by the Inbound Distributed Buffer Manager ASIC.
7. While the J-cells are being stored in memory, the Internet Processor ASIC receives the notification
cell and performs a route lookup in the forwarding table. The next-hop router along the path of the route and the outgoing interface on the router is determined. This next-hop information is stored in the notification cell, which now becomes the result cell.
8. The Internet Processor ASIC sends the result cell to the Outbound Distributed Buffer Manager ASIC, which examines the cell to locate the outgoing interface. The result cell is then sent to the appropriate FPC for queuing and transmission.
9. The I/O Manager ASIC queues the result cell and applies appropriate queuing mechanisms. When the result cell reaches the head of the queue, the I/O Manager ASIC requests the packet’s J-cells from the Outbound Distributed Buffer Manager ASIC.
10. The Outbound Distributed Buffer Manager ASIC copies the J-cells from the packet storage buffer and sends them to the I/O Manager ASIC on the outgoing FPC.
11. The I/O Manager ASIC re-forms the data packet into a single unit and alters any protocol TTL values. The ASIC then appends the appropriate Layer 2 header information and sends the packet to the PIC I/O Manager ASIC.
12. The PIC I/O Manager ASIC performs any link-layer duties, if required, and transmits the data packet out the router’s interface.
Multicast Packets
A Juniper Networks router handles multicast data packets in a very similar fashion to unicast packets. There is only one major difference between the two, so we won’t repeat the packet flow steps in detail here.
Refer back to Figure 1.4 and the steps outlined in the previous section, and focus on steps 7 and 8. When the Internet Processor ASIC performs its route lookup on a multicast packet, it often finds multiple next-hop interfaces in the forwarding table. Information about all the outgoing interfaces is placed in the result cell and sent to the Distributed Buffer Manager ASIC. This ASIC examines the result cell and finds several outgoing interfaces. It generates a copy of the result cell for each interface and sends those cells to the appropriate I/O Manager ASICs on the FPCs. The queuing and transmission of the multicast packets at this point then follows the unicast packet steps outlined previously.
Exception Packets
The Packet Forwarding Engine can’t process some data packets in your network in its normal fashion. A prime example of these packets is routing protocol updates addressed to the router itself. There is no outgoing interface for these packets; they should be sent to the Routing Engine instead. The CPU on the router’s control board handles this type of traffic, called an exception packet.
Other forms of exception packets include:
-- Packets addressed to the router, such as ICMP pings, Telnet, and SSH traffic
-- Packets requiring the generation of an ICMP error message, including traceroute responses and destination unreachable messages
-- Packets containing an IP Options field
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